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ROM contents and tools of the Floppy-Speeder Professional-DOS, Version 1

As with many other floppy speeders for the C64 and C1541, the Kernal ROM of the C64 and the DOS ROM of the C1541 needs to be replaced for Professional-DOS.
Firmware and tools download
Professional-DOS, Version 1 ROM files (28kB, replaced 2002-10-06)

ZIP-File with all the ROMs and tools discussed here in raw binary format. Each of the ROMs does not contain the typical CBM style load addresses at the beginning of the file (except for program files ending with .prg). They are meant for professional EPROM burners or Flash programmers (PC based).

Professional-DOS, Version 1 Kernal files (25kB, replaced 2002-10-06)

ZIP-Compressed D64 disk image with all the ROMs and tools discussed here in typical CBM style format. They are meant for direct use with eprom burners for the C64.
C64 Kernal ROM
With the first versions of Professional-DOS, many users got the ability to modify existing speeder firmware with a special ROM patch utility to create a C64 Kernal ROM their own. This way the user didn't need to learn other command sets, but could the already known of the old speeder.
For the Professional-DOS version presented here the C64 Kernal was missing since it arrived, but one patch utitlity could be found, that creates a Kernal out of an existing SpeedDOS floppy speeder system. This way a C64 Kernal for Professional-DOS Version 1 could be created. You can find this utility as well as the ready built C64 Kernal ROM in a ZIP archive below.
The EPROM of the drive expansion board doesn't not only contain the drive replacement ROM located in the C1541 memory map from 0xe000 to 0xffff. It also contains additional ROM code, that is mapped to the memory location 0x8000-0x9fff (this is only valid for Version 1). The floppy ROM located from 0xc000 to 0xdfff remains untouched.
When you insert the drive expansion board, you have to remove the main (upper) DOS ROM as the manual says, because the replacement ROM is already supplied with the board. Some logic of the board splits the 16KB EPROM (27128) into two parts and maps each half to another memory location of the drive's memory map. The EPROM adresses from 0x0000 to 0x1fff are mapped onto the drive's addresses from 0xe000 to 0xffff. EPROM adresses from 0x2000 to 0x3fff are mapped to the drive's addresses 0x8000 to 0x9fff.
The ROM code, that has been added, mainly contains fast GCR decoding routines as well as some big decoding tables. But these routines will not work without the special hardware extensions given by the drive expansion board. As far as the GCR decoding process could be revealed until now, the decoding routines only selects the right table and stores the decoded bytes. The hardware does the whole rest: splitting a byte into nibbles and decoding each nibble with the help of the big GCR tables. At each step, one of the nibbles is intermediately stored in an internal 4-Bit register for the next step. All you can see (if you disassemble the ROM) are many consecutive LDA and ORA instructions, that make no sense under normal circumstances, e.g. (to understand the comments, you probably would have to look at the PROM table and the functional description in the electronics section first):
902f 50 fe        bvc $902f
9031 b8           clv
9032 ae 01 1c     ldx $1c01

;  store the high nibble of X as new internal register value (NIRV)
9035 bd 00 81     lda $8100,x    ; preload: NIRV=Hi(X)

;  AH (address lines A[4..7])=current internal register value (CIRV),
;  NIRV=AL (address lines A[0..3])=low nibble of X
9038 bd 00 80     lda $8000,x    ; decode 1st nibble in Hi(CIRV)|Lo(X)
903b 50 fe        bvc $903b
903d b8           clv
903e ae 01 1c     ldx $1c01

;  AH=CIRV, NIRV=AL=high nibble of X
9041 1d 00 83     ora $8300,x    ; decode 2nd nibble in Hi(CIRV)|Hi(X)
9044 c5 39        cmp $39
9046 f0 03        beq $904b
9048 4c 7b 91     jmp $917b

;  AH=CIRV, NIRV=AL=low nibble of X
904b bd 00 84     lda $8400,x    ; decode 3rd nibble in Hi(CIRV)|Lo(X)
904e 50 fe        bvc $904e
9050 b8           clv
9051 ae 01 1c     ldx $1c01
9054 1d 00 87     ora $8700,x    ;
decode 4th nibble in Hi(CIRV)|Hi(X)
9057 85 1a        sta $1a
9059 bd 00 80     lda $8000,x    ;
preload: NIRV=Lo(X)
905c 50 fe        bvc $905c
905e b8           clv
905f ae 01 1c     ldx $1c01
9062 bd 00 81     lda $8100,x    ;
decode 5th nibble in Hi(CIRV)|Hi(X)
9065 1d 00 82     ora $8200,x    ; decode 6th nibble in Hi(CIRV)|Lo(X)
9068 85 19        sta $19
906a 45 1a        eor $1a
906c 85 1a        sta $1a
906e 50 fe        bvc $906e
9070 b8           clv
9071 ae 01 1c     ldx $1c01
9074 bd 00 85     lda $8500,x    ;
decode 7th nibble in Hi(CIRV)|Hi(X)
9077 1d 00 86     ora $8600,x    ; decode 8th nibble in Hi(CIRV)|Lo(X)
907a 85 18        sta $18
907c 45 1a        eor $1a
907e 85 1a        sta $1a
9080 50 fe        bvc $9080

;  decode next 5-byte GCR group into 4 normal bytes
9082 b8           clv
9083 ae 01 1c     ldx $1c01
9086 bd 00 81     lda $8100,x
9089 bd 00 80     lda $8000,x
908c 50 fe        bvc $908c
908e b8           clv
908f ae 01 1c     ldx $1c01
The first of the doubled LDA instructions above may be some initialization for the internal 4-Bit latch, the second one starts the decoding process of one GCR group (decoding 5 GCR bytes – 10 nibbles – into 4 normal bytes).

It does mess up your brain, how this is working, doesn't it?

By the way: The drive GCR table ROM cannot be read out with "M-R" floppy commands, because of the additional nibble dispatch hardware on the expansion board. To read out the floppy ROM you really need an EPROM burner or similar device.
C1541 additional RAM
The drive expansion board also brings an additional 8K static RAM into the drive's memory map. This 8K RAM is located at the addresses from 0xa000 to 0xbfff. Take note, that this is only valid for Version 1 of Professional-DOS. Later revisions mapped the extra ROM and RAM into the address space from 0x4000 to 0x7fff.


Wolfgang Moser, 2003-05-25,  ,  ("contact me" form disabled due to too high demand, sorry)